1 Ocak 2016 Konferans bildirisi Açık Erişim

Gursoy, Cemil Cem; Yildiz, Abdullah; Goren, Sezer

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{
  "@context": "https://schema.org/", 
  "@id": 111812, 
  "@type": "ScholarlyArticle", 
  "creator": [
    {
      "@type": "Person", 
      "affiliation": "Yeditepe Univ, Dept Comp Engn, Istanbul, Turkey", 
      "name": "Gursoy, Cemil Cem"
    }, 
    {
      "@type": "Person", 
      "affiliation": "Yeditepe Univ, Dept Comp Engn, Istanbul, Turkey", 
      "name": "Yildiz, Abdullah"
    }, 
    {
      "@type": "Person", 
      "affiliation": "Yeditepe Univ, Dept Comp Engn, Istanbul, Turkey", 
      "name": "Goren, Sezer"
    }
  ], 
  "datePublished": "2016-01-01", 
  "description": "Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application time while considering stuck-at, bridging and transition faults at the same time.", 
  "headline": "On optimization of multi-cycle tests for test quality and application time", 
  "identifier": 111812, 
  "image": "https://aperta.ulakbim.gov.tr/static/img/logo/aperta_logo_with_icon.svg", 
  "license": "http://www.opendefinition.org/licenses/cc-by", 
  "name": "On optimization of multi-cycle tests for test quality and application time", 
  "url": "https://aperta.ulakbim.gov.tr/record/111812"
}