1 Ocak 2016 Konferans bildirisi Açık Erişim

Gursoy, Cemil Cem; Yildiz, Abdullah; Goren, Sezer

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        "affiliation": "Yeditepe Univ, Dept Comp Engn, Istanbul, Turkey", 
        "name": "Gursoy, Cemil Cem"
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      {
        "affiliation": "Yeditepe Univ, Dept Comp Engn, Istanbul, Turkey", 
        "name": "Yildiz, Abdullah"
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        "affiliation": "Yeditepe Univ, Dept Comp Engn, Istanbul, Turkey", 
        "name": "Goren, Sezer"
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    "description": "Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application time while considering stuck-at, bridging and transition faults at the same time.", 
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      "title": "PROCEEDINGS OF 2016 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS)"
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    "title": "On optimization of multi-cycle tests for test quality and application time"
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