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Tools and Techniques for Implementation of Real-time Video Processing Algorithms

Levent, Vecdi Emre; Guzel, Aydin E.; Tosun, Mustafa; Buyukmihci, Mert; Aydin, Furkan; Goren, Sezer; Erbas, Cengiz; Akgun, Toygar; Ugurdag, H. Fatih


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  <identifier identifierType="URL">https://aperta.ulakbim.gov.tr/record/72903</identifier>
  <creators>
    <creator>
      <creatorName>Levent, Vecdi Emre</creatorName>
      <givenName>Vecdi Emre</givenName>
      <familyName>Levent</familyName>
      <affiliation>Ozyegin Univ, Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Guzel, Aydin E.</creatorName>
      <givenName>Aydin E.</givenName>
      <familyName>Guzel</familyName>
      <affiliation>Ozyegin Univ, Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Tosun, Mustafa</creatorName>
      <givenName>Mustafa</givenName>
      <familyName>Tosun</familyName>
      <affiliation>Ozyegin Univ, EEE, Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Buyukmihci, Mert</creatorName>
      <givenName>Mert</givenName>
      <familyName>Buyukmihci</familyName>
    </creator>
    <creator>
      <creatorName>Aydin, Furkan</creatorName>
      <givenName>Furkan</givenName>
      <familyName>Aydin</familyName>
      <affiliation>Ozyegin Univ, Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Goren, Sezer</creatorName>
      <givenName>Sezer</givenName>
      <familyName>Goren</familyName>
      <affiliation>Yeditepe Univ, Elect &amp; Elect Engn, Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Erbas, Cengiz</creatorName>
      <givenName>Cengiz</givenName>
      <familyName>Erbas</familyName>
      <affiliation>Aselsan, Ankara, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Akgun, Toygar</creatorName>
      <givenName>Toygar</givenName>
      <familyName>Akgun</familyName>
      <affiliation>Aselsan, Ankara, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Ugurdag, H. Fatih</creatorName>
      <givenName>H. Fatih</givenName>
      <familyName>Ugurdag</familyName>
      <affiliation>Ozyegin Univ, Istanbul, Turkey</affiliation>
    </creator>
  </creators>
  <titles>
    <title>Tools And Techniques For Implementation Of Real-Time Video Processing Algorithms</title>
  </titles>
  <publisher>Aperta</publisher>
  <publicationYear>2019</publicationYear>
  <dates>
    <date dateType="Issued">2019-01-01</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Journal article</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://aperta.ulakbim.gov.tr/record/72903</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1007/s11265-018-1402-7</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="http://www.opendefinition.org/licenses/cc-by">Creative Commons Attribution</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB 3.0, DRAM), high-level synthesis, RTL generation tools, synthesis automation as well as architectural concepts (e.g., nested pipelining), an architectural estimation tool, and verification methodology. The paper also discusses a specific use case to deploy the mentioned tools and techniques for hardware design of an optical flow algorithm. The paper shows that in a fairly short amount of time, we were able to implement 11 versions of the optical flow algorithm running on 3 different FPGAs (from 2 different vendors), while we generated and synthesized several thousand designs for architectural trade-off.</description>
  </descriptions>
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