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Levent, Vecdi Emre; Guzel, Aydin E.; Tosun, Mustafa; Buyukmihci, Mert; Aydin, Furkan; Goren, Sezer; Erbas, Cengiz; Akgun, Toygar; Ugurdag, H. Fatih
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB 3.0, DRAM), high-level synthesis, RTL generation tools, synthesis automation as well as architectural concepts (e.g., nested pipelining), an architectural estimation tool, and verification methodology. The paper also discusses a specific use case to deploy the mentioned tools and techniques for hardware design of an optical flow algorithm. The paper shows that in a fairly short amount of time, we were able to implement 11 versions of the optical flow algorithm running on 3 different FPGAs (from 2 different vendors), while we generated and synthesized several thousand designs for architectural trade-off.
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bib-4fa9a723-94d9-44bd-915f-4e4afd996dc3.txt
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Tekil görüntülenme | 44 |
Tekil indirme | 11 |