Konferans bildirisi Açık Erişim
Irmak, Hasan; Alachiotis, Nikolaos; Ziener, Daniel
<?xml version='1.0' encoding='utf-8'?> <resource xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://datacite.org/schema/kernel-4" xsi:schemaLocation="http://datacite.org/schema/kernel-4 http://schema.datacite.org/meta/kernel-4.1/metadata.xsd"> <identifier identifierType="URL">https://aperta.ulakbim.gov.tr/record/239292</identifier> <creators> <creator> <creatorName>Irmak, Hasan</creatorName> <givenName>Hasan</givenName> <familyName>Irmak</familyName> <affiliation>Univ Twente, Comp Architecture Embedded Syst, Enschede, Netherlands</affiliation> </creator> <creator> <creatorName>Alachiotis, Nikolaos</creatorName> <givenName>Nikolaos</givenName> <familyName>Alachiotis</familyName> <affiliation>Univ Twente, Comp Architecture Embedded Syst, Enschede, Netherlands</affiliation> </creator> <creator> <creatorName>Ziener, Daniel</creatorName> <givenName>Daniel</givenName> <familyName>Ziener</familyName> <affiliation>Tech Univ Ilmenau, Comp Architecture & Embedded Syst, Ilmenau, Germany</affiliation> </creator> </creators> <titles> <title>An Energy-Efficient Fpga-Based Convolutional Neural Network Implementation</title> </titles> <publisher>Aperta</publisher> <publicationYear>2021</publicationYear> <dates> <date dateType="Issued">2021-01-01</date> </dates> <resourceType resourceTypeGeneral="Text">Conference paper</resourceType> <alternateIdentifiers> <alternateIdentifier alternateIdentifierType="url">https://aperta.ulakbim.gov.tr/record/239292</alternateIdentifier> </alternateIdentifiers> <relatedIdentifiers> <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/SIU53274.2021.9477823</relatedIdentifier> </relatedIdentifiers> <rightsList> <rights rightsURI="http://www.opendefinition.org/licenses/cc-by">Creative Commons Attribution</rights> <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights> </rightsList> <descriptions> <description descriptionType="Abstract">Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded real-time applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.</description> </descriptions> </resource>
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