1 Ocak 2021 Dergi makalesi Açık Erişim

Aksoy, Levent; Akkan, Nihat; Sedef, Herman; Altun, Mustafa

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        "affiliation": "Istanbul Tech Univ, Dept Elect & Commun Engn, Emerging Circuits & Computat Grp, TR-34469 Istanbul, Turkey", 
        "name": "Aksoy, Levent"
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      {
        "affiliation": "Yildiz Tech Univ, Dept Elect & Commun Engn, TR-34220 Istanbul, Turkey", 
        "name": "Akkan, Nihat"
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      {
        "affiliation": "Yildiz Tech Univ, Dept Elect & Commun Engn, TR-34220 Istanbul, Turkey", 
        "name": "Sedef, Herman"
      }, 
      {
        "affiliation": "Istanbul Tech Univ, Dept Elect & Commun Engn, Emerging Circuits & Computat Grp, TR-34469 Istanbul, Turkey", 
        "name": "Altun, Mustafa"
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    "description": "Switching lattices, consisting of four-terminal switches, present an alternative structure for the realization of Boolean logic functions. Although promising algorithms have been introduced to find a realization of a logic function using a switching lattice with the fewest number of four-terminal switches, the delay of a switching lattice has not been examined yet. In this article, we generate a switching lattice using a recently proposed CMOS-compatible four-terminal device model and formulate the delay of a path in a switching lattice. It is observed that the delay of a design realizing a logic function on a switching lattice heavily depends on the number of four-terminal switches in the critical path. With this motivation, we introduce optimization algorithms, called PHAEDRA and TROADES, which can find the realization of a logic function on a switching lattice with the fewest number of switches under a delay constraint given in terms of the number of switches in the critical path. While PHAEDRA is a dichotomic search algorithm that can obtain solutions with a small number of switches on small size logic functions, TROADES is a divide-and-conquer method that can find a solution using less computational effort and can easily handle larger size logic functions with respect to PHAEDRA. The experimental results show that the proposed algorithms can reduce the delay of a lattice realization of a logic function significantly at a cost of an increase in the number of switches. They can explore alternative lattice realizations of a logic function by changing the delay constraint, enabling a designer to choose the one that fits best in an application.", 
    "doi": "10.1109/TCAD.2020.3035629", 
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      "issue": "10", 
      "pages": "2036-2048", 
      "title": "IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS", 
      "volume": "40"
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    "publication_date": "2021-01-01", 
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    "title": "Realization of Logic Functions Using Switching Lattices Under a Delay Constraint"
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