1 Ocak 2021 Dergi makalesi Açık Erişim

Aksoy, Levent; Akkan, Nihat; Sedef, Herman; Altun, Mustafa

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  <identifier identifierType="URL">https://aperta.ulakbim.gov.tr/record/237288</identifier>
  <creators>
    <creator>
      <creatorName>Aksoy, Levent</creatorName>
      <givenName>Levent</givenName>
      <familyName>Aksoy</familyName>
      <affiliation>Istanbul Tech Univ, Dept Elect &amp; Commun Engn, Emerging Circuits &amp; Computat Grp, TR-34469 Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Akkan, Nihat</creatorName>
      <givenName>Nihat</givenName>
      <familyName>Akkan</familyName>
      <affiliation>Yildiz Tech Univ, Dept Elect &amp; Commun Engn, TR-34220 Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Sedef, Herman</creatorName>
      <givenName>Herman</givenName>
      <familyName>Sedef</familyName>
      <affiliation>Yildiz Tech Univ, Dept Elect &amp; Commun Engn, TR-34220 Istanbul, Turkey</affiliation>
    </creator>
    <creator>
      <creatorName>Altun, Mustafa</creatorName>
      <givenName>Mustafa</givenName>
      <familyName>Altun</familyName>
      <affiliation>Istanbul Tech Univ, Dept Elect &amp; Commun Engn, Emerging Circuits &amp; Computat Grp, TR-34469 Istanbul, Turkey</affiliation>
    </creator>
  </creators>
  <titles>
    <title>Realization Of Logic Functions Using Switching Lattices Under A Delay Constraint</title>
  </titles>
  <publisher>Aperta</publisher>
  <publicationYear>2021</publicationYear>
  <dates>
    <date dateType="Issued">2021-01-01</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Journal article</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://aperta.ulakbim.gov.tr/record/237288</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/TCAD.2020.3035629</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="http://www.opendefinition.org/licenses/cc-by">Creative Commons Attribution</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">Switching lattices, consisting of four-terminal switches, present an alternative structure for the realization of Boolean logic functions. Although promising algorithms have been introduced to find a realization of a logic function using a switching lattice with the fewest number of four-terminal switches, the delay of a switching lattice has not been examined yet. In this article, we generate a switching lattice using a recently proposed CMOS-compatible four-terminal device model and formulate the delay of a path in a switching lattice. It is observed that the delay of a design realizing a logic function on a switching lattice heavily depends on the number of four-terminal switches in the critical path. With this motivation, we introduce optimization algorithms, called PHAEDRA and TROADES, which can find the realization of a logic function on a switching lattice with the fewest number of switches under a delay constraint given in terms of the number of switches in the critical path. While PHAEDRA is a dichotomic search algorithm that can obtain solutions with a small number of switches on small size logic functions, TROADES is a divide-and-conquer method that can find a solution using less computational effort and can easily handle larger size logic functions with respect to PHAEDRA. The experimental results show that the proposed algorithms can reduce the delay of a lattice realization of a logic function significantly at a cost of an increase in the number of switches. They can explore alternative lattice realizations of a logic function by changing the delay constraint, enabling a designer to choose the one that fits best in an application.</description>
  </descriptions>
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