FPGA Implementation of Layered Low Density Parity Check Error Correction Codes

In this study, Layered Low Density Parity Check (LDPC) Decoder algorithm in Error Correction Codes is implemented on FPGA. Firstly, Layered LDPC Decoder algorithm is designed with floating point in MATLAB, then fixed point model is developed. By testing Floating and Fixed point designs, transmitted information that is deformed by AWGN model is corrected by decoding iteratively. After this step, fixed point design is modelled in Verilog HDL. The design in Verilog HDL is matched with MATLAB model and then the Verilog HDL model is implemented on Xilinx Virtex 7 FPGA. Design that is implemented on FPGA has 280 MHz clock frequency and 25.426 Mbps data speed.