A new scalable hardware architecture for RSA algorithm

A new scalable systolic hardware architecture for RSA cryptosystems is presented. The kernel of the architecture can operate with different precision of inputs which enables making area-time tradeoff in design. The add-shift Montgomery algorithm is used for modular multiplication. Unlike previous approaches after add operation, the result is shifted to the previous systole to divide by radix. This simplifies the structure of processing elements. The R-L binary Montgomery exponentiation algorithm is used. The square and multiply operations are performed in parallel. The architecture is implemented in Xilinx Virtex-5 FPGA (Field Programmable Gate Array) chips for different radixes. The DSP48E slices in the FPGA chips are used to increase the throughput of the design. The results are compared with the literature. It is seen that the highest performance per area is obtained with the Radix-2(16) design.