An Area Efficient True Random Number Generator Based on Modified Ring Oscillators

True Random Number Generators (TRNGs) are used in but not limited to neural networks, Monte Carlo calculations and cryptography. Ring oscillator based designs are most common way of implementing random number generators on field-programmable gate arrays (FPGAs). This paper presents new method of implementation of two fully digital modified ring oscillator methods which utilize ring oscillators' wake-up and shut-down time uncertainties. With the added uncertainties, overall entropy is increased, and fulfilling binary random data is obtained using fewer ring oscillators. This makes TRNG area efficient by reducing the number of gates. This method is based on two existing modified ring oscillator models. The circuit is implemented in the FPGA and tested it on National Institute of Standards and Technology (NIST) 800-22 test suite without using any post processing methods. It was shown that wake-up model uses 25%, and sleep model uses 50% fewer ring oscillators compared to classical ring oscillator based TRNGs.