High-Speed Random Number Generator Design in 22nm FD-SOI Process

We present the design of a chaos based Truly Random Number Generator (TRNG) which benefits from the advantages introduced by deep submicron FD-SOI technology. Proposed design is simulated using Cadence IC Design tools and GLOBALFOUNDRIES 22FDX process design kit simulation libraries for both forward back-biasing (FBB) and reverse back-biasing (RBB) options. Effects of different back-biasing voltage levels are demonstrated. Simulation results show that the proposed circuit offers significant advantages over previously reported implementations of chaos based TRNGs, in terms of operating frequency, power consumption and required chip area.