Ring Oscillator Based Random Number Generator Using Wake-up and Shut-down Uncertainties

This paper presents a random number generation circuit based on an irregular sampling of modified ring oscillators. Most of the true random number generators in Field Programmable Gate Arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. Whereas random number generation using modified ring oscillator models incorporate timing jitter with metastability. Metastability is caused by turning ring oscillator on and off periodically. Ring goes into metastability state before turning completely on. This entropy can be extracted by using wake-up or shut-down uncertainty methods. After extraction, random bits generated by an irregular sampling of the high-frequency clock using the output of the ring oscillator. The Virtex 5 xc5v1x110t FPGA is used for generating bitstreams and these are tested on National Institute of Standards and Technology (NIST) 800-22 test suite without using any post-processing methods. It is observed that wake-up and shut-down methods are successful, and all methods have fulfilled the tests.