Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder

This paper presents the set of optimizations for the efficient implementation of lossless JPEG-LS encoder. Given approaches are not only based on digital design techniques but also emerged from scrutinizing the regularity of the algorithm. Although it is well known for the low complexity, former designs have significant divergences hence varying performances. In this context, critical design issues of JPEG-LS encoder and trade-offs are discussed in detailed benchmark. FPGA implementation results suggest that encoder with the proposed optimizations outperforms the state-of-art counterparts in terms of hardware cost and throughput.