FPGA IMPLEMENTATION OF TURBO DECODERS USING BCJR ALGORITHM

The most difficult design issue for turbo codes, which is the most recent and successful channel coding method to approach the channel capacity limit, is the design of the iterative decoders which perform calculations for all possible states of the encoders. BCJR (MAP) algorithm, which is used for turbo decoders, embodies complex mathematical operations such as division, exponential and logarithm calculations. Therefore, BCJR algorithm was avoided and the sub-optimal derivatives of this algorithm such as Log-MAP and Max-Log-MAP were preferred for turbo decoder implementations. BCJR algorithm was reformulated and wrapped into a suitable structure for FPGA implementations at previous works [1]. Reformulated BCJR algorithm is implemented in this work. Complex mathematical operations which run slowly on hardware (division, exponential and logarithm calculations) are read from look-up-tables and high performance calculation structures are established. Implemented system is verified through simulations. It is observed that the BER performance obtained is better than the Log-MAP algorithm as expected.