An Efficient Hardware Implementation of PRI De-Interleaver and Estimator

Efficiency of an Electronics Warfare (EW) system relies on the effectiveness of the pulse de-interleaver and time of arrival estimation of the next coming target pulses. Thus, de-interleave process needs to be completed with minimum knowledge of the environment and accomplished in low latency. In this work, we presented a hardware implementation of a real-time Pulse Repetition Interval (PRI) de-interleaving algorithm in FPGA. In the first version (named as Type-1), the system can decode limited number of emitters in an environment. In the second version (named as Type-2), we increase the ability of the de-interleaver by using the similar mechanism of the human brain in the visual search condition. This enhancement enables the system to increase its efficiency and number of emitters the deinterleaver can handle at the same time.