Cause Mining and Controller Synthesis with STL

Formal control of cyber-physical systems allows for synthesis of control strategies from rich specifications. However, the classes of systems that the formal approaches can be applied to is limited due to the computational complexity. Furthermore, the synthesis problem becomes even harder when non -determinism or stochasticity is considered. In this work, we propose an alternative approach. First, we mark the unwanted events on the traces of the system and generate a controllable cause representing these events as a Signal Temporal Logic (STL) formula. Then, we synthesize a controller to avoid the satisfaction of this formula. Our approach is applicable to any system with finitely many control choices. While we can not guarantee correctness, we show on examples that the proposed approach reduces the number of the unwanted events.