Low-Complexity MIMO MMSE Receiver with Performance Enhancement via Coordinate Interleaving

Multiple-input multiple-output (MIMO) Minimum mean-square error (MMSE) receivers are widely adopted in the latest communication standards and reducing the complexity of these receivers while preserving the error performance is highly desirable. In this work, we study the error performance and implementation complexity of MIMO MMSE receivers when combined with a coordinate interleaved signal space diversity (SSD) technique. Contrary to the well-known trade-off between the error performance and implementation complexity, the proposed system leads to a considerably simplified MIMO MMSE receiver with significant performance gains when compared to the original MIMO MMSE receiver. Unlike the standard MIMO MMSE receiver, the proposed coordinate interleaved technique induces a block diagonal transmit correlation matrix providing both performance enhancement and complexity reduction. The results show that the error performance can be improved more than 10dB with up to 71% computational complexity reduction. The complexity comparison between the original and proposed approaches is also verified by means of field-programmable gate array (FPGA) implementation.