Improving Combinational Circuit Resilience against Soft Errors via Selective Resource Allocation

Combinational circuits have become more vulnerable to soft errors (SEs) in each CMOS technology generation. Most of the prior studies use hardware redundancy in an attempt to harden the circuits against errors. However, redundancy increases the area and power consumption. Furthermore, the design constraints may not allow adding redundant resources to the final circuit. In this paper, we present a genetic algorithm(GA)- based design method to increase the reliability of combinational circuits. In this method, we use different versions of the same resources, each having different area, latency, and reliability values. The goal of GA-based method is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 19.90% (14.50% on average) reliability improvement against a heuristic method with no additional area overhead.