Yayınlanmış 1 Ocak 2009
| Sürüm v1
Dergi makalesi
Açık
Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms
Oluşturanlar
- 1. Kocaeli Univ, Dept Elect & Telecommun Engn, Kocaeli Univ Lab Image & Signal Proc, TR-41040 Kocaeli, Turkey
- 2. Sabanci Univ, Fac Engn & Nat Sci, TR-34956 Istanbul, Turkey
Açıklama
In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.
Dosyalar
bib-c44eb944-72d3-4ba7-8027-82fbad726cac.txt
Dosyalar
(187 Bytes)
| Ad | Boyut | Hepisini indir |
|---|---|---|
|
md5:e9e0c3b7d8d226d25a94ad1065007db4
|
187 Bytes | Ön İzleme İndir |