Published January 1, 2018
| Version v1
Conference paper
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A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs
Creators
- 1. Istanbul Tech Univ, Dept Elect & Commun Engn, Istanbul, Turkey
- 2. Girne Amer Univ, Dept Elect & Elect Engn, Kyrenia, Turkey
Description
This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 mu m x 360 mu m silicon area, is realized in a SiGe BiCMOS 0.13 mu m process.
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