A High Speed 180 nm CMOS Cryogenic SAR ADC

In this paper, an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) which can be operated between room temperature and 77K has been designed for transceivers which is aimed to be used in space communications. The design has been accomplished through UMC 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed SAR ADC offers high speed and high linearity due to its integer-based digital-to-analog converter architecture. Reference clock signal of the SAR ADC has been generated via a charge pump-based phase locked loop (CP-PLL). At room temperature, the proposed SAR ADC accomplishes an effective number of bits (ENOB) of 7.7, and a signal to noise and distortion ratio (SNDR) of 48.15 dB. At 77 K, it achieves an ENOB of 7.8 and a SNDR of 48.71 dB. As the temperature becomes lower, it can be observed that the performance of the proposed SAR ADC improves noticeably.