Implementation of a Linear LN-TIA with PMOS Resistors in a T-network Configuration

This paper introduces the measurement of the previously published low-noise transimpedance amplifier (LN-TIA(1)) and the simulation results of the LN-TIA2 with improved linearity. Both LN-TIAs are based on a T-network feedback architecture that incorporates tunable PMOS resistors. The proposed LN-TIA(2) achieves a linearity and dynamic range enhancement exceeding +30 dB, without compromising the noise floor performance at 18 kHz. The LN-TIA(2) performs wide output dynamic range so that the differential peak-to-peak output voltage can reach up to 8 V, corresponding to 63 dB SNDR. It achieves a transimpedance gain ranging from 100 k Omega to 125 M Omega and operates across a frequency range of 100 Hz to 18 kHz. Implemented in a 0.7 mu m, 2-metal CMOS process, the overall chip occupies a silicon area of 1170 mu m x 1332 mu m.