Chip-Level Surface Patterning Solutions Towards High-Throughput, Parallel Surface Modulation of 1D Nanomaterials

Surface patterning of the suspended 1D nanostructures allows manipulation of their surface, transport, and electrical properties. However, resistless and chip-level patterning approaches are needed to achieve property manipulation of multiple devices simultaneously in a high throughput and parallel manner. In this work, we report on developing a stencil-based resistless and high throughput surface patterning approach for potential surface modulation of suspended sub-micron Si nanowires. A two-point alignment approach achieves complete chip-level alignment between the stencil and nanowire chip, where the chip can ideally accommodate any designed device density. Chips housing 16 devices are surface patterned, and performance evaluation reveals a pattern registration accuracy of 1.1 +/- 0.53 mu m and rotational misalignment of 0.3 mrad. Gold-based surface patterning is conducted to demonstrate property modulation, showing a resistance change of up to 50% for Si nanowires. The approach offers the potential for manipulating 1D nanomaterial properties to design high-performance biochemical and gas sensors.