Logic Locking-Based FPGA System Design for Third-Party IP Protection

In the FPGA (Field Programmable Gate Arrays) development environment, IP (Intellectual Property) is frequently used to implement standard or customized operations quickly and reliably without requiring labor resources. In cases where IP developers do not transfer their intellectual property rights, methods are implemented with the developer or FPGA manufacturer to protect these rights. Logic locking method is a concept developed to secure the chip design against hardware trojans or elements involved in the chip manufacturing production stages. This paper proposes a cryptographic solution based on logic locking to ensure that the functional structure of the IP cannot be obtained by treating the FPGA manufacturer as secure.