Voltage and frequency reliant interface traps and their lifetimes of the MPS structures interlayered with CdTe:PVA via the admittance method

In this work, to gain detailed information about the electrical characteristics, interface traps (Dit), and their lifetimes (tau) of the metal-polymer-semiconductor (MPS) type structures, admittance measurements performed in wide frequency and voltage ranges have been utilized. At the outset, the intercept, and slope of the 1/C2 vs V curve were used to unveil the density of acceptor-atoms (NA), depletion-layer width (WD), and barrier-height (phi B). All these parameters show strong frequency dependence with the effect of the Dit, interlayer, interface, and dipole polarization, especially at low and moderate frequencies. Therefore, Dit and tau were determined from the admittance method. The measured C -G/omega vs V curves were adjusted for higher frequencies taking into account the series-resistance effect. Experimental results indicate the strong effect of the Rs value on the capacitance and conductance values only at the accumulation-regime for higher-frequencies whereas the Dit effect in both inversion and depletion regimes for lower-frequencies.