Laser Lithography of Monolithically-Integrated Multi-Level Microchannels in Silicon

The trend toward ever-increased speeds for microelectronics is challenged by the emergence of heat-wall, leading to the faltering of Moore's Law. A potential solution may be integrating microfluidic channels into silicon (Si), to deliver controlled amounts of cooling fluid and regulate hot spots. Such meandering microfluidic channels within other transparent materials already played significant roles, including in biomedical and sensor applications; however, analogous channel architectures do not exist in Si. Here, a novel method is proposed to fabricate buried microchannel arrays monolithically integrated into Si, without altering the wafer surface. A two-step, laser-assisted subtractive removal method is exploited, enabling fully-buried multi-level architectures, with control on the channel port geometry, depth, curvature, and aspect ratio. The selective removal rate is 750 mu m per h per channel, and the channel inner-wall roughness is 230 nm. The method preserves top wafer surface roughness of 2 nm, with significant potential for 3D integrated systems.

A novel method is proposed to fabricate buried microchannel arrays monolithically integrated into silicon wafers. This advance preserves the top wafer surface after fabrication, and provides a potential direction toward on-chip/in-chip integrated systems. image