A Compact SiGe BiCMOS Distributed Power Amplifier in 5-24 GHz

This brief presents the design and implementation of a compact and highly efficient distributed power amplifier in IHP's 0.13-mu m SiGe BiCMOS process. The proposed design focuses on improving the drawbacks of the distributed topology, such as high area, low efficiency, and low gain. 3-stage distributed cascode topology is used with small inductors in ATLs to reduce the chip area and parasitic losses. An RF choke inductor is utilized at the base line to increase the gain and output power. The 3-dB bandwidth is from 5GHz to 24GHz where input and output are matched to 50O. Measurements showed that the maximum output 1-dB compression point is 16.4dBm, and the minimum is 14.4dBm with a peak gain of 19.5dB. Peak PAE and total area with pads are 33.5% and 0.63mm(2), respectively. To the best of the authors' knowledge, the lowest area among the published silicon-based distributed power amplifiers are achieved.