Implementation of Neuro-Inspired Arithmetic and Logic Circuits

Artificial neurons provide a new way of computation for neuro-inspired algorithms, and the abilities may efficiently solve the challenges. We propose implementations of logic gates (and, or, xor, and Majority), full adder, full subtractor, even parity generator, and 2-bit multiplier circuit formed by Josephson junction-based soma (JJ-Soma) and standard Rapid Single Flux Quantum (SFQ) digital library cells. The designed circuits execute ultra-high-speed operations without a clock signal, and they are capable of processing parallel or time-sliced operations. The combination of JJ-Soma cells and SFQ cells creates the potential models for the arithmetic logic unit devices with a small on-chip area, high operating speed, and pipeline structures for microprocessors. In this study, the previously optimized JJ-Soma circuits have low power consumption and high computational speed where the firing rates for two-pulse and three-pulse threshold circuits were designed to be 50 and 15 GHz with about 10(-19) J/spike energy level. The proposed circuits, fabricated with a commercial foundry service, have been implemented and demonstrated experimentally.