Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm*

This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 mu m x 1300 mu m, in a SiGe BiCMOS 0.13 mu m process. The clock generation system occupies 400 mu m x 360 mu m silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm x 5 mm QFN32 package and assembled onto an FR4 board.