A Computation and Power Reduction Technique for H.264 Intra Prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a technique for reducing the amount of computations performed by 11.264 intra prediction algorithm. For, each intra prediction equation, the proposed technique compares the pixels used in this prediction equation. If the pixels used in a prediction equation are equal, this prediction equation is simplified significantly. By exploiting the equality of the pixels used in prediction equations, the proposed technique reduces the amount of computations performed by 4x4 luminance prediction modes up to 78% with a small comparison overhead. The proposed technique does not affect the PSNR and bitrate. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex II FPGA using Xilinx)(Power, and it reduced the power consumption of this hardware up to 13.7%.