A time-interleaved ADC calibration technique for spectrum monitoring applications

A fully background estimation and calibration technique to reduce the spur powers caused by time-interleaved ADC architecture is presented. The estimations of mismatches are succeeded using easily generated calibration signals. The implementation details for the mismatch estimations and calibrations are provided using a 2.8 GSPS ADC and a FPGA device. Continuous operation of the spectrum monitoring applications is allowed while the mismatch estimation and the calibration process in progress. The offset mismatch calibration is realized using an adder circuit at the background and more than 10 dB spur power reduction is obtained from the proposed method. A digital multiplier circuit is used to realize the gain calibration. The timing skew calibration is fulfilled by the addition of a small offset to the DDS (Direct Digital Synthesizer) phase offset of DDC (Digital Down Converter). It is possible to get more than 6 dB power reduction at some critical spur signals after the application of proposed timing mismatch calibration technique when a single tone sine wave input is applied.