Random Number Generators Based on Metastable Behavior in Double-Scroll Chaotic Attractors

This paper presents the numerical analysis, circuit implementation and simulation of a random number generator (RNG) exploiting the metastable behavior arising in a double scroll chaotic attractor. Random bits are generated by sampling a regular clock signal at times when a jump between scrolls of the chaotic attractor occurs. The double-scroll chaotic oscillator used in this study is implemented using mosfet transistors and metal-insulator-metal (mim) capacitors at 65nm TSMC process. The overall monolithic RNG circuit consists of a chaotic attractor, a Schmitt trigger and a dual edge triggered D flip-flop. The RNG circuit is simulated in time domain using Cadence Analog Design Environment. Then to generate the output bit stream, a regular clock signal is sampled when the chaotic signal jumps from one of the scrolls to the other representing the metastable characteristic of chaos. The event of jump between scrolls is detected using the mosfet based Schmitt trigger and an irregular clock signal is generated which is used to sample a regular clock signal by using a dual-edge triggered D flip-flop to generate RNG output. The generated bit stream is demonstrated to satisfy the NIST 80022 statistical randomness test suite. The layout of the proposed RNG is also given along with the circuit schematic. The area of the RNG is approximately 0.004 mm(2), the power consumption is 30 mu W, and the data throughput is approximately 0.72 Mbps.