Duty Cycle Correction Circuit and Its Application for High Speed Random Number Generation

This paper presents a wake-up & shut-down ring oscillator based Random Number Generator (RNG) together with a new method of duty cycle correction circuit for cryptographic applications more specifically irregular sampling of regular waveform method based True Random Number Generators (TRNGs). The proposed circuit is composed of fully digital elements and contains only one D type flip-flop, one inverter, one buffer, and one XOR gate. The bias at the one-zero balance that occurs in irregular sampling of regular waveform based RNGs due to the regular clock's duty cycle is avoided by discarding the sampled data at the problematic duty cycle regions. The improvement provided with the proposed circuit is shown by applying the method to a Random Number Generator based on irregular sampling of regular waveform method. The irregular clock is generated by employing wake-up and shut-down ring oscillators. The speed of the sampling is reduced by downsampling the irregular signal. All of the circuits mentioned in this paper are implemented in Xilinx Zynq7000 FPGA. Furthermore, NIST 800-22 test suite is used to test all of the designs. Data sets of one million bits are collected with a UART module. All the NIST 800-22 test suite requirements are satisfied with the duty cycle correction applied RNG. The proposed circuit improves the throughput of the wake-up&shut-down RNG 12.3 times. Furthermore, the proposed circuit can be used with any RNG based on irregular sampling of regular waveform method.