Analog circuit architecture for max and min pooling methods on image

This paper proposes a voltage mode analog circuit structure for max and min pooling methods used in convolutional neural network (CNN) in order to reduce the size of the image. The circuit architecture is based on WTA and LTA circuits with 4-input and 9-input since 2 x 2 and 3 x 3 max/min pooling operations are carried out. WTA and LTA circuits have a quite simple structure and consist of operational amplifiers (OPAMP) and MOS transistors. In analysis section, the size of a 300 x 300-pixels image is successfully reduced by using max and min pooling methods. The performance of the introduced max and min pooling circuits is justified with the help of quality measurement parameters such as structural similarity index metric (SSIM), mean absolute error (MAE), mean squared error (MSE) and peak signal to noise ratio (PSNR). Correlation coefficient analyses have also been carried out to see the similarity between the images generated by pooling operations and the original image. In addition, image histograms have been presented in order to show the differences between max and min pooling operations. TSMC CMOS 0.18 mu m process model is used to simulate the suggested analog structure.