40 GS/s 5 bit Time Interleaved Analog to Digital Converter in 0.18 mu m SiGe BiCMOS Process

This paper presents the transistor-level schematics, layout design considerations, and post-layout simulation of a four-channel 5 bit 40 GS/s BiCMOS Time-Interleaved Analog to Digital Converter (TI-ADC) by using 0.18 mu m SiGe BiCMOS technology library. This proposed structure has been propounded as a solution for systems that require a high sampling rate for the systems such as wireless and high-speed data communication systems, application of the internet of things and instrumentation and measurement systems, etc. The designed TI-ADC consists of Track and Hold Amplifier (THA) based switch-emitter follower which is not affected by temperature variation, 5 bit Flash ADC and 4 x 1 multiplexer circuit. The supply voltage of the THA circuit and the other circuits in the proposed TI-ADC are 5 and 3.3 V, respectively. For the simulation, the analog input of TI-ADC is selected as a ramp-shaped signal with amplitude in a range of 1.60 to 2.60 V. The post-layout simulation results show that, with a 153.8 MHz analog input and 40 GHz sampling rate, the DNL and INL values are measured -0.21 LSB and 0.26 LSB, -0.2 LSB and 0.35 LSB, respectively. The post-simulations indicate that the effective number of bits (ENOB), active chip area and signal-to-noise ratio (SNR) are 4.37 bits, (0.430 x 0.412) mm(2) and 28.01 dB respectively, with a bandwidth of 50 MHz, a sampling frequency of 40 GHz. The total power consumption of TI-ADC is 2.6 W.