Design and evaluation of schemes for computing sum of squares in fixed point

Several schemes for computing the sum of squares for fixed point numbers are designed, synthesized, and evaluated in this study. The schemes use radix-2 folding, radix-4 folding, and radix-4 dual recoding approaches for squaring. The schemes have been modeled in hardware description language, simulated, and synthesized using Cadence SOC81 in 45 nm and 90 nm libraries and with Mentor Graphics Leonardo Spectrum for 180 nm. We show delay and area for 16-, 24-, and 32-bit operands. After hard-wire and software optimizations, it is seen that schemes with radix-4 give better results, especially in area.