Design of a fully-static differential low-power CMOS flip-flop

A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [1], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure showed to be consuming less power and occupying smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures.