Error correction capability aware BCH implementation for NAND flash memories in Earth observation satellites

In this paper, a parallel FPGA architecture implementing BCH error correction for NAND flash memories in storage modules of Earth observation satellites (EOS) is presented. In order to satisfy the error correction requirements of NAND flash memories the designed module is capable of correcting 4 erroneous bits in code words (CW) of 4148 bits using shortened BCH (4148, 4096) algorithm. Besides the standard BCH encoding and decoding procedure a code selection module is added to the architecture to guess whether or not the CW has more than 4 errors. If more than 4 errors occurs in the CW the architecture understands that the CW is uncorrectable and does not try to change any bits which will most probably inject more errors to the CW. The design is implemented on a XC7VX485T FPGA from Virtex 7 series of Xilinx and with a 300 MHz system clock, it is capable of encoding and decoding information at 4,78GBits/sec.