A Complexity Reduction Method for Successive Cancellation List Decoding

This brief introduces a hardware complexity reduction method for successive cancellation list (SCL) decoders. Specifically, we propose to use a sorting scheme so that L paths with smallest path metrics are also sorted according to their path indexes for path pruning. We prove that such sorting scheme reduces the input number of multiplexers in any hardware implementation of SCL decoding from L to (L/2+1) without any changes in the decoding latency. Field programmable gate array (FPGA) implementations show that the proposed method achieves significant gain in hardware consumptions, especially for large list sizes and block lengths.